A Comprehensive Study of Hot-Carrier Effects in Body-Tied FinFETs

Hot-carrier effects in body-tied FinFETs are investigated for the first time. Device degradation by hotcarrier injection (HCI) becomes significant as a fin width (channel thickness) increases. There are two competing conditions to degrade the device by HCI: VG (<0.5VDD) at ISUBmax and VG=VD=VDD. Interface trap generation is dominant at VG at ISUBmax and oxide trap are dominant at VG=VD=VDD. At the narrow fin width, the device is more degraded by the interface trap generation (VG at ISUBmax) rather than by the oxide trap (VG=VD=VDD). However, both mechanisms equally degrade the devices at the wide fin. INTRODUCTION FinFETs showed superior scalability for nano-scale CMOS with a simple fabrication process [1-2]. In the previous fully-depleted SOI FinFETs [3], the major difficulty was in finding the worst hot-carrier stress because a substrate current (ISUB) can not be measured due to its floating body. In this work, hot-carrier-injection (HCI) effects were carefully studied at the conditions: VG@ISUBmax and VG=VD for various fin widths. It is well known that trap generation at Si-SiO2 interface leads the device degradation at VG@ISUBmax (VG/VD~0.5), and trapped charges inside the gate oxide governs the device reliability at high VG (VG/VD~1) in planar bulk-MOSFETs. To find the condition maximizing ISUB, the ratio of VG/VD was measured for different fin widths. The mechanism of device degradation was investigated in terms of stress condition dependence and fin width dependence for the first time. This study can give us impact on determining the worst hot-carrier stress condition in SOI FinFETs, which show more robustness to short-channel effects and a superior scalability. EXPERIMENTS The process details were reported elsewhere [2]. A schematic of the body-tied FinFET is shown in Fig. 1. The gate length is 100nm, the fin widths are in the range of 20nm to 100nm, and the gate oxide thickness is 1.7nm. A threshold voltage (VT) was read at 100nA of drain current at VD=50mV, and on-state current (ION) was measured at VG-VT=1V and VD=1V as key device parameters. All measured data are from n-channel FinFETs. RESULTS AND DISCUSSIONS Fig. 2 shows the typical bell-shaped ISUB, which depends on the fin width (WFin) in the body-tied FinFETs. Beyond a critical VG to cause ISUBmax, ISUB is effectively suppressed by the high gate field at the narrow fin whereas it is not sufficiently diminished at the wide fin. As the fin width increases, ISUBmax becomes large, and VG/VD ratio at ISUBmax becomes close to 1 as shown in Fig. 2 and Fig. 3. Fig. 4 represents an impact ionization rate, ISUB/ID [4]. It is large at the wide fin, which is consistent with the previous report [3]. The device degradation by HCI is more significant at the wide fin. Because, as VG increased, ISUB/ID is not quickly suppressed at the wide fin than at the narrow fin. A saturated drain voltage (VDsat) was measured and plotted to VG for various fin widths in Fig. 5. It is large at the narrow fin. Since the maximum lateral channel field is expressed as ( ) / m D Dsat E V V l = − , the impact ionization rate, which is a strong exponential function of Em, is decreased due to large VDsat at the narrow fin. In addition to ISUB, IG is measured as well in Fig. 6. It is large at the wide fin, which shows the same trend as the previous report [5]. To find the worst case hot-carrier stress condition, ISUB and IG are measured and compared at both VG@ISUBmax and VG=VD on the same plot for various fin widths in Fig. 7. ISUB quickly reduces at VG=VD as the fin width decreases, however, ISUB is weakly depending on the fin width at VG @ISUBmax. IG rapidly decreases as the fin width reduces at VG@ISUBmax while IG is insensitive to the fin width at VG=VD. Discrepancy between both conditions tends to be zero at the wide fin. So, both of the interface trap generation and the oxide trapped charges deteriorate the device reliability equally at certain wide fin with. But, at narrow fin width, VG@ISUBmax and VG=VD are competing which condition degrades the device by HCI more. It is crucial to determine the worst hot-carrier stress condition at the narrow fin because a worst degradation mechanism is unclear. But, it is less crucial to find the worst stress condition at the wide fin because both mechanisms equally affect the device degradation. To verify which is the worst hot carrier stress condition and to compare hot carrier immunity with the fin width, hot carrier stress was conducted with two competing conditions at WFin=20nm and WFin=70nm. Fig. 7 shows that ION degrades by HCI as the stress time increases for the different stress conditions as well as the two fin widths. Degradation of ION is always large at the wide fin with both stress conditions. Either stress condition equally degrades ION at the wide fin. At the narrow fin, it is worthwhile to note that the reduction of ION is larger at VG@ISUBmax than at VG=VD, and difference of ION between two conditions becomes increasing. This suggests that the interface trap generation lead the hot-carrier induced device degradation at the narrow fin with the stress condition, VG @ISUBmax. Fig. 9 shows threshold voltage (VT) degradation for various drain voltages after 10,000 second stress. It duplicates the same scenario, which is similar to the trend in ION degradation. CONCLUSIONS In this work, the hot-carrier effects of the body-tied FinFETs are comprehensively studied for various stress conditions for the first time. It is observed that VG/VD ratio at ISUBmax becomes large and ISUB increases as the fin width broadens. IG is also found to be increased as the fin width increases. At the narrow fin, the device degradation is led by the interface trap generation mechanism at the condition, VG to cause peak ISUB. At the wide fin, however, the oxide trapped charges at VG=VD condition and the interface trap generation at VG@ISUBmax are equally important. This work provides insight on finding the worst stress conditions to affect the hot-carrier induced device degradation in the SOI FinFETs. ACKNOWLEDGEMENT This work was supported by Samsung Electronics Co., Ltd. Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials, Kobe, 2005, -876B-8-4 pp.876-877